Frequency locked loop, clock recovery circuit and receiver

ABSTRACT

A frequency locked loop comprising a controllable oscillator ( 1 ) and a control signal generator ( 2 ) for generating a control signal (Sc) for the oscillator ( 1 ) from a reference signal (Sref) and an output signal (So) from the oscillator ( 1 ). The frequency locked loop is characterized in that, the control signal generator ( 2 ) comprises a first chain including a high pass filter ( 21 ) and a non-linear processing unit ( 22 ) for generating a first intermediate signal (S 1 ) from the reference signal (Sref), a second chain including a high pass filter ( 23 ) and a non-linear processing unit ( 24 ) for generating a second intermediate signal (S 2 ) from the output signal (So) of the controllable oscillator ( 1 ), a combination unit ( 25 ) for generating a third intermediary signal (S 3 ) from the first (S 1 ) and the second intermediary signal (S 2 ), a low-pass filter ( 26 ) for providing the control signal (Sc) in response to the third intermediary signal (S 3 ).

The invention relates to a frequency locked loop comprising acontrollable oscillator and a control signal generator for generating acontrol signal for the oscillator from a reference signal and an outputsignal from the oscillator.

Such a frequency locked loop is known from EP 395 109. In the knownfrequency locked loop the control signal generator comprises a dividerhaving an input for receiving the output signal of the oscillator. Anoutput signal of the divider is coupled to a first input of a phasecomparator. A second input thereof is coupled to a frequency generatorwhich generates a fixed frequency. An output of the phase comparator iscoupled to a low-pass filter via a buffer. The output of the phasecomparator is directly coupled to a fine control input of theoscillator. The output of the phase comparator is also coupled to afirst input of a voltage comparator. The latter has a second inputcoupled to a reference voltage. The output of the voltage comparator iscoupled via a buffer and a second low-pass filter to a course controlinput of the oscillator.

It is a purpose of the invention to provide a frequency locked loophaving a simplified frequency detection. According to the invention, thefrequency locked loop is characterized in that the control signalgenerator comprises

-   -   a first chain including a high pass filter and a non-linear        processing unit for generating a first intermediate signal from        a reference signal,    -   a second chain including a high pass filter and a non-linear        processing unit for generating a second intermediate signal from        the output signal of the controllable oscillator,    -   a combination unit for generating a third intermediary signal        from the first and the second intermediary signal,    -   a low-pass filter for providing the control signal in response        to the third intermediary signal.

The frequency locked loop according to the invention allows for a fastresponse to variations in the frequency of the input signal.

The embodiments of the invention according to claim 2 and claim 3 makeit possible to change the ratio between the frequency of the outputsignal and the frequency of the reference signal without using afrequency divider. For the frequency of the output signal can beincreased by increasing the magnification of the gain stage whichcouples the combination unit to the non-linear processing unit of thefirst chain. Likewise the frequency of the output signal can beincreased by decreasing the magnification of the gain stage whichcouples the combination unit to the non-linear processing unit of thesecond chain. The magnification can be a factor greater than 1, but alsoa factor less than or equal to 1.

These and other aspects of the invention are described in more detailwith reference to the drawing. Therein:

FIG. 1 shows a frequency locked loop according to the invention,

FIG. 2 shows in more detail a part of FIG. 1,

FIG. 3 shows in more detail a part of FIG. 2,

FIG. 4 shows in more detail another part of FIG. 1,

FIG. 5 shows in more detail a further part of FIG. 1,

FIG. 6 shows a clock recovery circuit comprising the frequency lockedloop of FIG. 1,

FIG. 7 shows a receiver comprising the clock recovery circuit of FIG. 6,

FIG. 8 shows an alternative embodiment of the frequency locked loopaccording to the invention.

FIG. 1 shows a frequency locked loop comprising a controllableoscillator 1 and a control signal generator 2 for generating a controlsignal Sc for the oscillator 1 from a reference signal Sref and anoutput signal So from the oscillator 1. The frequency locked loopaccording to the invention is characterized in that the control signalgenerator 2 comprises a first chain including a high pass filter 21 anda non-linear processing unit 22 for generating a first intermediatesignal S1 from a reference signal. The control signal generator 2further comprises a second chain including a high pass filter 23 and anon-linear processing unit 24 for generating a second intermediatesignal S2 from the output signal So of the controllable oscillator 1.The control signal generator 2 further comprises a combination unit 25for generating a third intermediary signal S3 from the first S1 and thesecond intermediary signal S2. The control signal generator 2 comprisesa low-pass filter 26 for providing the control signal Sc in response tothe third intermediary signal S3.

In the embodiment shown in FIG. 1, the high pass filters 21 and 23 aredifferentiators, and the low pass filter 26 is an integrator. Thenon-linear processing units 22 are absolute value detectors.

FIG. 2 shows an embodiment of the differentiator 21 of the frequencylocked loop. The differentiator 23 is identical thereto. Thedifferentiator 21 shown therein comprises a first and a second circuitmodule 210, 212, which are mutually coupled via a capacitive element C.The capacitive element C is coupled at a first side to the node 21 f ofcircuit module 210, and at a second side to node 21 g of circuit module212. The circuit modules 210 and 212 are each coupled to a respectiveinput 21 a and 21 b, and have outputs 21 d, 21 e, which are coupled acommon output 21 c which is coupled to a current source I1.

In the following the designation “transistor” will refer to acontrollable semiconductor element such as a bipolar transistor or aunipolar transistor (MOSFET). Main electrodes are understood to be theemitter and collector of a bipolar transistor, or the source and thedrain of a unipolar transistor. The wording control electrode is used todenote the base of a bipolar transistor or the gate of a uniplartransistor.

FIG. 3 shows a preferred embodiment of the first circuit module 210. Theother circuit module 212 is identical thereto. Therein nodes 21 b, 21 gand 21 e take the place of nodes 21 a, 21 f and 21 d. The circuit module210 shown therein comprises a first, a second, and a third chain. Thefirst chain includes a resistive element R0 which couples a first mainelectrode of a first transistor Q0 to a first line of constant voltage.Another main electrode of the first transistor Q0 is coupled to acurrent source I3 in a node N1. The node is also coupled to the input 21a for receiving an input signal current i_(in). The second chaincomprises a second transistor Q1 having a first main electrode coupledto the first line of constant voltage, and a second main electrodecoupled to a second current source I2. The second main electrode of thesecond transistor Q1 is also coupled to a control electrode of the firsttransistor Q0 and to the node 21 f. A control electrode of the secondtransistor Q1 is coupled to the first main electrode of the firsttransistor Q0. The third chain of the circuit comprises a third and afourth transistor. The third transistor Q3 has a first main electrodecoupled to the first line of constant voltage and a second mainelectrode coupled to a first main electrode of the fourth transistor Q2.The fourth transistor Q2 has a second main electrode coupled to theoutput 21 d. The third chain is bridged by the main current path of afifth transistor Q8. The latter has its control electrode connected tothe second main electrode of the third transistor.

The circuit operates as follows. If a signal current i_(in) is appliedat the input nodes this results in a voltage V over the capacitor Caccording to: $\begin{matrix}{V = \frac{i_{i\quad n}}{gm}} & (1)\end{matrix}$The voltage V over the capacitor corresponds to a current i_(c) throughthe capacitor, such that:i_(c)=s.C.V  (2)This current i_(c) is approximately equal to the current i₁ provided bythe controllable semiconductor element Q1, hencei₁≈s.C.V  (3)Furthermore, in the circuit shown in FIG. 3 the following relationapplies to the base-emitter voltages V_(be1), V_(be2), V_(be3), V_(be8)of Q1, Q2, Q3 and Q8 respectively:V _(be1) +V _(be2) =V _(be3) +V _(be8)  (4)This implies for the currents i₁, i₂ and i₀:i₁.i₂≈i₂.i₀ or i₁≈i₀  (5)Combining (3), (1) and (5) it follows: $\begin{matrix}{i_{0} \approx {{s \cdot \frac{C}{gm}}i_{i\quad n}}} & (6)\end{matrix}$

The modulus circuit 22 is shown in more detail in FIG. 4. The moduluscircuit 24 is identical thereto. The circuit shown therein comprises afirst circuit portion 221 for calculating the sign of the input signaland a second circuit portion 222 for multiplying the sign of the inputsignal with the momentaneous value of the input signal. The input signalis differential, including a first current Io(1+x) and a second currentIo(1+x). The input signal is applied both to the first circuit portionand to the second circuit portion. The first portion comprises a latchQ1, Q2, Q3, Q4. The inputs thereof are formed by the control electrodesof the semiconductor elements Q1 and Q2. The inputs are coupled to amain electrode of a further semiconductor element Q11, Q12. Thesemiconductor elements Q12, Q1, Q2, Q11 form a translinear loop, whichensures that a copy of the input current flows in the transistors Q1 andQ2. The transistors Q3 and Q4 are connected such that any imbalance inthe collectors Q1 and Q2 is amplified and finally the current IBIAS willflow either in the transistor Q9 or in the transistor Q10, dependent onthe sign of the input current. Multiplying the input current with itssign in the second portion an output signal is obtained which isrepresentative for the modulus of the input signal. In order to avoidhysterezis, two fixed current sources can be added in the emitters of Q9and Q10.

FIG. 5 shows a possible implementation of the integrator 26, a modifiedversion of the class AB integrator from E. Seevinck, “Compandingcurrent-mode integrator: A new circuit principle for continuous-timemonolithic filters”, Electron. Lett., vol. 26, no. 24, pp. 2046-2047,November 1990.It can be shown that: $\begin{matrix}{{xI}_{0} = {{CV}_{T}\frac{\mathbb{d}z}{\mathbb{d}t}}} & (1)\end{matrix}$Hence, from (1) results that the differential current flowing in theoutput transistors Q7 and Q8 amounts:$z = {\frac{I_{0}}{{CV}_{T}}{\int{x{\mathbb{d}t}}}}$

FIG. 6 shows a clock recovery circuit 31 which comprises a controllableoscillator 1. The controllable oscillator 1 is part of a frequencylocked loop further including the control signal generator 2. Thecontrollable oscillator 1 has a course tuning port 1 a which is coupledto the control signal generator 2. The control signal generator receivesa reference signal Sref from a reference signal generator 27, such as acrystal. The controllable oscillator 1 also forms part of a phase lockedloop which comprises a phase detector 35 for generating a phasedifference signal Sd which is indicative for a phase difference betweenthe input signal Sin and a feedback signal Sb. The feedback signal Sfbis obtained by a frequency divider 38 from the output signal of thecontrollable oscillator 1.

FIG. 7 shows a receiver 3 for a fibre-optic channel 5. The receivercomprises an input 33 for receiving an input signal Sin from an sensor 4which is coupled to the fibre-optic channel 5. A clock recovery circuit31 according to the invention is coupled to the input 33 for receivingsaid input signal Sin as the reference signal. A data recovery circuit32 is coupled to the clock recovery circuit 31 and to the input 33. Thedata recovery circuit generates a digital output signal Sout in responseto the input signal Sin, and an output signal Cl of the clock recoverycircuit 31. The digital output signal Sout is provided at an output 34of the receiver 3.

FIG. 8 shows an alternative embodiment of the frequency locked loopcircuit according to the invention. In FIG. 1, elements corresponding tothose of FIG. 1 have a reference number which is 100 higher. Thefrequency locked loop circuit shown therein is characterized in that thecombination unit 125 is coupled to the non-linear processing unit 122 ofthe first chain with a gain stage 125 a. In the embodiment showntherein, the combination unit 125 is coupled to the non-linearprocessing unit 124 of the second chain with a gain stage 125 b too. Bychanging the gain of the stages, the ratio between the frequency of thereference signal Sref, and the frequency of the output signal So can bechanged. For example, the frequency of the output signal So can beincreased by increasing the magnification of the gain stage 125 a, whichcouples the combination unit 125 to the non-linear processing unit 122of the first chain. Likewise the frequency of the output signal So canbe increased by decreasing the magnification of the gain stage 125 bwhich couples the combination unit 125 to the non-linear processing unit124 of the second chain. The magnification can be a factor greater than1, but also a factor less than or equal to 1.

1. A frequency locked loop comprising a controllable oscillator (1) anda control signal generator (2) for generating a control signal (Sc) forthe oscillator (1) from a reference signal (Sref) and an output signal(So) from the oscillator (1), characterized in that, the control signalgenerator (2) comprises: a first chain including a high pass filter (21)and a non-linear processing unit (22) for generating a firstintermediate signal (S1) from the reference signal (Sref), a secondchain including a high pays filter (23) and a non-linear processing unit(24) for generating a second intermediate signal (S2) from the outputsignal (So) of the controllable oscillator (1), a combination unit (25)for generating a third intermediary signal (S3) from the first (S1) andthe second intermediary signal (S2), a low-pass filter (26) forproviding the control signal (Sc) in response to the third intermediarysignal (S3).
 2. A frequency locked loop circuit according to claim 1,characterized in that the combination unit (125) is coupled to thenon-linear processing unit (122) of the first chain with a gain stage(125 a).
 3. A frequency locked loop circuit according to claim 1,characterized in that the combination unit (125) is coupled to thenon-linear processing unit (124) of the second chain with a gain stag(125 b).
 4. A frequency locked loop according to claim 1, characterizedin that the high pass filter (21, 23) is a differentiator.
 5. Afrequency locked loop loop according to claim 1, characterized in thatthe low pass filter (26) is an integrator.
 6. A frequency locked loopaccording to claim 1, characterize in that the non-linear processingunit (22, 24) is an absolute value detector.
 7. A frequency locked loopaccording to claim 4, wherein the differentiator comprises a first (210)and a second circuit module (212) which are mutually coupled via acapacitive element (C).
 8. A frequency locked loop according to claim 4,characterized in that the differentiator comprises a translinear loop(Q2, Q3, Q4, Q5).
 9. A frequency locked loop according to claim 6,characterized in that he absolute value detector (21) comprises a firstcircuit portion (221) for calculating the sign of the input signal and asecond circuit portion (222) for multiplying the sign of the inputsignal with the momentaneous value of the input signal.
 10. A clockrecovery circuit comprising a controllable oscillator (1) which both ispart of a frequency locked loop as claimed in claim 1 and of a phaselocked loop.
 11. A receiver (3) for a fibre-optic channel (5) comprisingan input (33) for receiving an input signal (Sin) from an sensor (4)which is coupled to the fibre-optic channel (5), a clock recoverycircuit (31) according to claim 10 coupled to the input (33) forreceiving said input signal (Sin) as a reference signal, a data recovercircuit (32) coupled to said clock recovery circuit (31) and the input(33), for generating a digital output signal (Sout) in response to theinput signal (Sin), and an output signal (CL) of the clock recoverycircuit (31), an output (34) or providing the digital output signal(Sout).